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Low-Level Programming news and engineering summaries

Low-level programming discussions covering assembly, memory management, systems programming, and hardware interaction from developer communities.

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I Ported Mac OS X to the Nintendo Wii
01Wednesday, April 8, 2026

I Ported Mac OS X to the Nintendo Wii

A developer successfully ported Mac OS X 10.0 Cheetah to the Nintendo Wii. By writing a custom bootloader, patching the Mach-O kernel, and developing IOKit drivers for the Wii's Hollywood SoC, the project achieved a functional desktop environment. This effort involved solving complex challenges like endianness, framebuffer rendering, and USB hardware communication.

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Hardware researcher spins up 'CPU deoptimization' project to find the slowest single x86 instruction, creates hall of shame — worst offender takes 198 billion cycles spanning 62 seconds to execute
02Saturday, August 8, 2026

Hardware researcher spins up 'CPU deoptimization' project to find the slowest single x86 instruction, creates hall of shame — worst offender takes 198 billion cycles spanning 62 seconds to execute

Hardware researcher Christopher Domas created the CPU Deoptimization leaderboard to identify the slowest x86 instructions. By manipulating PCIe fabric through MMIO and state restoration, he achieved a record-breaking 198 billion cycle latency (62 seconds) for the xrstore64 instruction. This project highlights deep architecture vulnerabilities and provides a unique, tongue-in-cheek perspective on low-level performance bottlenecks.

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Storing 2 bytes of data in your Logitech mouse
03Saturday, March 21, 2026

Storing 2 bytes of data in your Logitech mouse

A developer successfully used the Logitech MX Vertical mouse as a tiny, persistent storage device by hacking its HID++ protocol. By writing arbitrary two-byte data into the DPI register, they demonstrated that the mouse maintains state across devices. The project highlights reverse engineering, firmware communication, and understanding OS-level hardware management through experimental technical exploration.

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Assembly Hall of Shame
04Thursday, August 6, 2026

Assembly Hall of Shame

The Assembly Hall of Shame is a project by Christopher Domas that identifies the slowest possible single instructions on x86 architectures. By deliberately triggering microcode assists, hardware traps, or saturating PCIe fabric with high-latency MMIO transactions, it reveals extreme performance penalties, with the record-holding 'fxrstor64' instruction taking over 198 billion cycles to complete.

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Defeating a 40-year-old copy protection dongle
05Sunday, February 1, 2026

Defeating a 40-year-old copy protection dongle

In a unique case of software archaeology, a researcher successfully bypassed hardware-based copy protection for a legacy RPG (Report Program Generator) II compiler used by an accounting firm. The firm was incredibly still running Windows 98 in 2026 to execute 40-year-old software requiring a physical dongle on a parallel port. By using the Reko disassembler to analyze 16-bit x86 executables, the researcher identified a specific 0x90-byte code segment responsible for dongle communication. Analysis revealed that the routine returned a constant value in the BX register regardless of input. Through brute-force testing within DosBox, the constant was identified as 7606h. Applying a four-byte assembly patch (MOV BX, 7606; RETF) successfully emulated the dongle presence, allowing the software—and its compiler—to run on modern emulators without the original hardware.

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The gold standard of optimization: A look under the hood of RollerCoaster Tycoon
06Sunday, March 22, 2026

The gold standard of optimization: A look under the hood of RollerCoaster Tycoon

RollerCoaster Tycoon remains a benchmark for game performance, largely due to Chris Sawyer’s expert use of Assembly and aggressive low-level optimizations. By balancing technical constraints with design choices—such as clever pathfinding limitations and simplifying complex agent interactions—Sawyer prioritized engine efficiency, creating a seamless simulation that holds up decades later.

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Atari 2600 Raiders of the Lost Ark source code completely disassembled and reverse engineered. Every line fully commented.
07Monday, February 9, 2026

Atari 2600 Raiders of the Lost Ark source code completely disassembled and reverse engineered. Every line fully commented.

This repository provides a comprehensive reverse-engineered source code analysis of the 1982 Atari 2600 classic, Raiders of the Lost Ark, originally designed by Howard Scott Warshaw. The analysis detail includes the disassembly of 8KB of ROM code across two banks, explaining how the 6502 assembly manages the hardware limitations of the Atari Television Interface Adaptor (TIA). Key technical features explored include the bank-switching mechanism using zero-page RAM trampolines, the division of game logic across TV signal phases (VSYNC, VBLANK, Kernel, and Overscan), and the specific rendering kernels for rooms like the Thieves' Den and the Ark Room. The project also documents unique programming tricks such as using bit 7 of sprite data for inline TIA register modification and the logic behind inventory management, collision detection, and the scoring system.

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Spaghettifying DRAM
08Thursday, August 13, 2026

Spaghettifying DRAM

Christopher Domas’s skitter-creek-bath-salts research demonstrates how modifying undocumented AMD Family 16h DRAM-controller address transformations can create aliases to protected memory. Using cache/TLB coordination and GF(2) linear algebra with z3, the toolchain reportedly reads or writes PSP, SMRAM, C6 state, and microcode stored in DRAM, exposing limits of higher-level isolation mechanisms.

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A 3rd World Embedded Engineer Responds to "RISC-V They Should Have Known Better"
09Sunday, August 16, 2026

A 3rd World Embedded Engineer Responds to "RISC-V They Should Have Known Better"

Armstrong Subero challenges Dmitry Grinberg’s criticism of RISC-V, acknowledging flaws in extensions and encoding but arguing they matter less than affordability, availability, and openness. Using CH32, Baochip, and OrangePi examples, he shows one ISA scaling from ultra-cheap MCUs to protected Linux-class systems, unlike ARM’s licensed product boundaries, enabling global education and experimentation.

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USB for Software Developers: An introduction to writing userspace USB drivers
10Tuesday, April 7, 2026

USB for Software Developers: An introduction to writing userspace USB drivers

Writing USB drivers is accessible without deep kernel knowledge, thanks to userspace libraries like libusb. This guide explains USB enumeration, endpoints, and descriptors using an Android phone in Fastboot mode. By understanding device identification and transfer types (Control, Bulk, Interrupt, Isochronous), developers can create functional drivers in userspace, mirroring simple network socket communication.

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Direct Win32 API, Weird-Shaped Windows, and Why They Mostly Disappeared
11Friday, April 10, 2026

Direct Win32 API, Weird-Shaped Windows, and Why They Mostly Disappeared

Modern Windows apps, often built on memory-heavy web frameworks, have lost the unique visual identity of the Win32 era. This technical analysis explores how raw Win32 API enables non-rectangular, custom-shaped, and animated windows. While challenging to implement, this low-level control offers a powerful alternative to generic, bloated desktop software, restoring creative freedom to application interface design.

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Every Byte Matters
12Monday, June 1, 2026

Every Byte Matters

Performance optimization requires understanding hardware-level data access. By shifting from an Array of Structs to a Struct of Arrays, developers can improve cache utilization. Aligning data structures with CPU cache line sizes and minimizing working set sizes significantly reduces memory latency, especially in random access scenarios where CPU prefetching is ineffective.

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Zig proposes introducing an actually memory safe (unlike Rust) compilation mode inspired by Fil-C at ~1-6x performance penalty
13Monday, July 20, 2026

Zig proposes introducing an actually memory safe (unlike Rust) compilation mode inspired by Fil-C at ~1-6x performance penalty

Zig proposes a new 'fil' ABI inspired by Fil-C to provide full memory safety for applications, including C/C++ dependencies, without an 'unsafe' escape hatch. This approach uses invisicaps to track pointer provenance and metadata. While promising for high-assurance security, it presents ongoing debates regarding architectural alignment with Zig's explicit memory management, potential runtime overhead, and internal ABI complexity.

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Dav2d
14Sunday, May 31, 2026

Dav2d

VideoLAN has introduced dav2d, a fast, open-source software decoder for the new AV2 video codec. Building on the success of the dav1d AV1 decoder, dav2d aims to provide a high-performance, portable implementation to support ecosystem adoption before dedicated hardware becomes available. The project is currently feature-complete and undergoing active optimization for x86, ARM, and RISC-V architectures.

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Your process' memory is a file: The underappreciated gem that is /proc/<pid>/mem
15Monday, June 1, 2026

Your process' memory is a file: The underappreciated gem that is /proc/<pid>/mem

In Linux, /proc/<pid>/mem acts as a file interface for a process's virtual memory. By using pread() or pwrite() with specific offsets, developers can directly read or modify another process's memory. This elegant approach provides a simpler alternative to the complex ptrace() system calls for tasks like memory analysis and data recovery.

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Zig Libc
16Saturday, January 31, 2026

Zig Libc

The Zig programming language's devlog for 2026 highlights a significant architectural transition involving the zig libc subproject. Led by Andrew Kelley and contributors, the project aims to replace vendored C source files with Zig standard library wrappers. This initiative has already removed approximately 250 C source files, moving toward a goal of total independence from third-party C dependencies. Key benefits of this transition include improved compilation speeds, reduced binary sizes due to better static linking, and a smaller installation footprint. Furthermore, by sharing a Zig Compilation Unit (ZCU) instead of using separate static archives, the compiler can perform optimizations across the libc boundary similar to front-end Link-Time Optimization (LTO). This shift also opens future possibilities for resource leak detection and integrating libc I/O calls directly into event loops like io_uring.

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Fixing a Bricked Framework Laptop
17Sunday, August 16, 2026

Fixing a Bricked Framework Laptop

A failed BIOS 3.20 update bricked an out-of-warranty Framework Laptop 13 AMD Ryzen 7040 Series. Framework offered only a costly motherboard replacement, so the author used a CH347 USB programmer, 1.8 V level shifter, pogo-pin probe, and flashrom to restore the BIOS for about US$20. The experience exposes serious shortcomings in repairability, recovery design, documentation, and data governance.

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Asahi Linux Progress Report: Linux 7.2
18Wednesday, August 26, 2026

Asahi Linux Progress Report: Linux 7.2

Asahi Linux’s latest report details major Apple Silicon advances: a UEFI Runtime Services-based PSCI conduit improves CPU power management, while m1n1 now supports SPTM/GXF emulation for XNU on M4+. M3 support nears release, and M4/M5 gain NVMe and PCIe. AVD video decoding, VA-API integration, and Interchange direct scanout improve multimedia efficiency; upstreaming continues.

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Let's see Paul Allen's SIMD CSV parser
19Friday, March 20, 2026

Let's see Paul Allen's SIMD CSV parser

This post explains how to build a high-performance CSV parser using SIMD techniques. By processing data in 16-64 byte chunks, the parser utilizes vectorized classification and bitwise operations to detect structural characters. These methods, including lookup tables and carryless multiplication, enable branchless, parallel parsing, significantly improving throughput for large datasets.

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BarraCUDA Open-source CUDA compiler targeting AMD GPUs
20Monday, February 16, 2026

BarraCUDA Open-source CUDA compiler targeting AMD GPUs

BarraCUDA is an open-source, C99-based CUDA compiler that targets AMD GFX11 (RDNA 3) GPUs without LLVM dependencies. It compiles .cu files directly into ELF binaries, featuring a custom intermediate representation and a hand-written instruction selector. Supporting core CUDA features like atomics and warp intrinsics, it offers a lightweight alternative to traditional GPU toolchains.

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